Semiconductor devices are used in a wide range of fields including the consumer field. With strong demand for reduction in size and weight as well as increase in functions of various products using the semiconductor device, recent years have seen a further increasing trend to higher integration and higher-speed operation. In particular, to address higher-speed operation of products using the semiconductor device, the semiconductor device handles higher-frequency signals. In such a high-frequency signal region, noise produces a notable effect on signal transmission, and therefore it is highly important to deal with such noise. In a general design, a capacitive component (bypass capacitor) is mounted at a stage previous to an input to/output from a semiconductor element, thereby reducing the effect of noise to ensure stable high-frequency characteristics.
FIGS. 20A and 20B illustrate an example of mounting a capacitive component of a conventional semiconductor device. The semiconductor device 20 shown in the figures has a wiring pattern included in an integrated circuit formed on a wiring-side surface of a semiconductor element 21. The wiring pattern includes an electrode portion (element electrode, not shown) having projecting electrodes (bumps) 23 previously formed by, for example, ball bonding or plating. The semiconductor element 21 and a circuit board 22 are positioned such that the bumps 23 are opposed to their corresponding board electrodes 24 of the circuit board 22, and the bumps 23 are joined to the board electrodes 24 by placing the semiconductor element 21 on the circuit board 22. In this manner, the semiconductor device 20 is formed. In addition, a capacitive component 25 is mounted on an input/output wire for the semiconductor element 21 on the circuit board 22, thereby ensuring stable high-frequency characteristics.
However, the demand for size reduction of products using the semiconductor device requires further size reduction of the circuit board, making it increasingly difficult to mount the capacitive component on the input/output wire for the semiconductor element on the circuit board. In particular, as the functionality of the semiconductor element increases, the number of input/output terminals is tremendously increased, while the demand for size reduction of the semiconductor element requires a number of input/output terminals to be provided in a smaller area. Therefore, the wiring pitch for input/output terminals is further reduced, making it increasingly difficult to mount capacitive components on the circuit board.
Here, to eliminate the effect of noise on the semiconductor element, the capacitive component is preferably positioned as close to the semiconductor element as possible. However, if the semiconductor element is further enhanced in speed in the future, providing the capacitive component in a position close to the semiconductor element is expected to become further difficult because there is a limit in shortening wires to be arranged. Specifically, if wires for providing capacitive components are lengthened, the wires also pick up noise, impairing high-frequency characteristics and the stability thereof. Therefore, such wires are required to be as short as possible.
In this regard, for example, Patent Document 1 proposes to structure capacitors by forming dielectric layers on top of bumps for connecting element electrodes of a semiconductor element and board electrodes of a circuit board (see FIG. 1 of Patent Document 1).
Also, Patent Document 2 proposes to provide a capacitive film between electrodes and an uppermost wiring layer in a silicon board having multi-level wiring layers (see FIG. 1 of Patent Document 2).
Also, Patent Document 3 proposes to provide capacitance components by forming space between bumps and electrodes opposed thereto (see FIG. 1 of Patent Document 3).
Patent Document 1: Japanese Laid-Open Patent Publication No. 6-224257
Patent Document 2: Japanese Laid-Open Patent Publication No. 2007-250760
Patent Document 3: Japanese Laid-Open Patent Publication No. 2003-59966